module count4(out,reset,clk);
input  wire reset, clk;
output reg  [3:0] out;

always @(posedge clk) begin 
    if(reset) out <= 4'b0;
    else begin 
        out <= out + 4'b1;
    end
end
endmodule

`timescale 1ns/1ns
module coun4_tp;
reg clk,reset; //测试输入信号定义为 reg 型
wire[3:0] out; //测试输出信号定义为 wire 型
parameter DELY=100;

count4 mycount(out,reset,clk); //调用测试对象

always #(DELY/2) clk = ~clk; //产生时钟波形

initial begin //激励信号定义
    clk = 0;
    reset = 0;
    #DELY reset = 1;
    #DELY reset = 0;
    #2000 $finish;
end

//定义结果显示格式
initial $monitor($time,,,"clk=%d reset=%d out=%d", clk, reset,out);

endmodule